The present invention relates to semiconductor power device technology and more particularly to improved trench vertical MOSFET devices and fabrication processes for forming such devices.
Semiconductor packages are well known in the art. These packages can sometimes include one or more semiconductor devices, such as an integrated circuit (IC) device, die or chip. The IC devices can include electronic circuits that have been manufactured on a substrate made of semiconductor material. The circuits are made using many known semiconductor processing techniques such as deposition, etching, photolithography, annealing, doping and diffusion. Silicon wafers are typically used as the substrate on which these IC devices are formed.
An example of a semiconductor device is a metal oxide semiconductor field effect transistor (MOSFET) device, which is used in numerous electronic apparatuses including power supplies, automotive electronics, computers and battery powered devices like mobile phones. MOSFET devices can be used in a variety of applications such as switches that connect power supplies to particular electronic devices having a load. MOSFET devices can be formed in a trench that has been etched into a substrate or onto an epitaxial layer that has been deposited onto a substrate.
MOSFET devices operate by applying an appropriate voltage to a gate electrode of a MOSFET device which turns the device ON and forms a channel connecting a source and a drain of the MOSFET allowing a current to flow. Once the MOSFET device is turned on, the relationship between the current and the voltage is nearly linear which means that the device behaves like a resistor. In transistors, including MOSFET devices, it is desirable to have low drain-to-source resistance RDS(on) while the transistor is on.
Vertical MOSFET devices typically try to achieve low RDS(on) by placing the drain on a surface which is opposite the surface of the source contact. By placing the drain on the surface opposite the source contact, the conduction path for current is reduced, which causes the RDS(on) to be reduced. However, placing the drain and drain contact on a surface which is opposite (and different) to the surface that the source contact is placed, makes it difficult to package the transistor, especially for Wafer Level Chip Scale Packaging (WLCSP), because electrical connections must be supplied to both sides of the package. When using WLCSP to package transistors it is necessary to place all the contacts including the source contact, drain contact and gate contact on the same side of the package. This type of configuration allows easy connection to circuit board traces using solder balls on the one surface of the WLCSP that are connected to each of the transistor terminals.
Since the RDS(on) of vertical transistors are optimized when the drain contacts and the source contacts are placed on opposite surfaces and WLCSP is optimized when all the contacts are on the same surface, it is not desirable to use WLCSP to package vertical transistors. Therefore, what is needed is a system and method that allows for using a vertical transistor with all the contacts on one side while still maintaining excellent electrical properties with low RDS(on).